This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-372974, filed on Dec. 6, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device using a multilayer wiring structure, and a method of manufacturing the same.
2. Related Art
Recently, large scale integrated circuits (hereinafter also referred to as xe2x80x9cLSIsxe2x80x9d) are facing the problem of the limitation in speeding up. In a conventional LSI, the speed-up of the entire LSI has been achieved by inhibiting a gate delay to speed up transistors. However, in such a conventional LSI having an operating frequency of 1 GHz or more, a wiring delay may have ooccured, which inhibits the speed-up of the LSI. Further, as the miniaturization of LSIs has proceeded, the distance between adjacent wirings has been reduced. As a result, interference between signal lines has become noticeable. Accordingly, attempts have been made to inhibit wiring delay by the use of the material technology, in which conventional Al alloy wiring and SiO2 insulating films are replaced by Cu wiring having a low resistivity and interlayer insulating films having a low permittivity.
However, although it is possible to inhibit RC delay, which is proportional to the product of wiring resistance R and wiring capacitance C, with the above-described improve in material, it is difficult to eliminate the influence of wiring inductance L. Especially, in a long wiring between circuit blocks, etc., the influence of wiring inductance increases because of the long length of the wiring, so that the influence of LC becomes more dominant than the influence of RC delay. In order to eliminate such an influence, the use of a microstrip line structure taken into consideration for a long wiring.
FIG. 33 shows a structure of a conventional semiconductor device having multilayer wiring and microstrip structure. This conventional semiconductor device has the following multilayer wiring structure: an insulating layer 901 is formed on a semiconductor substrate 900, on which devices not shown (for example, transistors) are formed; an insulating layer 902 is formed on the insulating layer 901; a metal layer 903 serving as a grounding electrode is formed 16 on the insulating layer 902; signal lines 905 are formed on the metal layer 903 via an insulating layer 904; the signal lines 905 are covered by an insulating layer 906; and a metal layer composed of grounding electrodes, an insulating layer, a signal line layer, etc., which are not shown, are formed on the insulating layer 906. In the microstrip line structure thus constituted, the signal lines 905 are sandwiched by the plane grounding electrode 903 and the power supply electrode, which is effective to reduce the influence of LC.
However, in the microstrip line structure as shown in FIG. 33 using the plane grounding electrode 903, since lines of electric field and magnetic field (electromagnetic field) directed from the signal lines 905 to the grounding electrode 903 are formed, as shown in FIG. 34, interference between vertically adjacent signal lines is inhibited. However, since the degree of the expansion of the electric flux lines and the magnetic field lines are large, the electric flux lines and the magnetic field lines reach horizontally adjacent signal lines. Accordingly, it is not possible to inhibit interference between horizontally adjacent signal lines.
Thus, in a microstrip line structure, as the wiring pitch is reduced due to miniaturization, the influence of the horizontally adjacent lines are increased. Accordingly, this structure has a problem that it cannot be applied to further miniaturization.
A semiconductor device according to an aspect of the present invention includes: a signal line, through which a signal having a desired frequency f0 passes, formed on a semiconductor substrate,; and a differential signal line through which a signal in opposite phase to the signal passes, or which is connected to a ground power supply, the signal line and the differential signal line being laminated via an insulating layer so as to be substantially in parallel with each other, and an actual wiring length l of the signal line being longer than a wiring length l0 determined by the following equation       l    0    =                              L          C                +                                                            R                2                            +                              8                ⁢                                  π                  2                                ⁢                                  f                  0                  2                                ⁢                                  L                  2                                                                    4              ⁢                              π                2                            ⁢                              f                0                2                            ⁢                              C                2                                                                          R          2                +                  4          ⁢                      π            2                    ⁢                      f            0            2                    ⁢                      L            2                              
where R represents a resistance component, L represents an inductance component, and C represent a capacitance component per unit length of the signal line in such a case that the differential signal line does not exist.
A method of manufacturing a semiconductor device according to a first aspect of the present invention includes: forming a first conductive layer on a semiconductor substrate; forming an insulating layer on the first conductive layer; forming a second conductive layer on the insulating layer; and pattering the second conductive layer, the insulating layer, and the first conductive layer at a time to form a first wiring from the first conductive layer, and to form a second wiring from the second conductive layer.
A method of manufacturing a semiconductor device according to a second aspect of the present invention includes: forming a groove in a first insulating layer formed on a semiconductor substrate; forming a first wiring by filling the groove with a wiring material; forming a second insulating layer covering the first wiring; forming a third insulating layer on the second insulating layer; forming a second wiring by forming an opening extending to the second insulating layer through the third insulating layer at a position corresponding to the first wiring, and filling the opening with a wiring material.
A method of manufacturing a semiconductor device according to a third aspect of the present invention includes: forming a groove in a first insulating layer formed on a semiconductor substrate; forming a first wiring layer covering sides and a bottom of the groove; and forming a second wiring layer in the groove via a second insulating layer so as to cover the first wiring layer.